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Physical Design Engineer

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✴️ Location: Country
Origin URL (viola_origin_url=https://pliops.com/open-jobs/co/vlsi-hardware/A7.A15/physical-design-engineer/all)
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Physical Design Engineer

Created:

Jul 18, 2023, 11:21 PM

Location

Ramat Gan, Tel Aviv District, Israel, 5250606

Organization

Pliops
Similar vacancies
Pliops
Ramat Gan, Tel Aviv District, Israel, 5250606

Physical Design Engineer

Description

About The Position

Who we are?

We are a growing startup company that changing the Storage Processor world, founded in 2017, and led by executives from industry leaders.

Pliops’ Storage Processor (PSP) is a hardware-based storage accelerator that enables cloud and enterprise customers to offload and accelerate data-intensive workloads using just a fraction of the computational load and power.

Pliops storage processor dramatically increases the number of transactions per second and expands capacity for the most demanding applications.

Pliops was recently named as one of the 10 hottest semiconductor startups in 2020 by CRN and its storage processors are shipping to select customers. The company has raised $115M to date from leading global investors including State of Mind Ventures, Viola Ventures, Intel Capital, KDT, SoftBank Ventures Asia, NVIDIA, Expon Capital, Western Digital, Xilinx and Sweetwood Capital.

To find out more about us, you can click on this link below:

https://www.calcalist.co.il/internet/articles/0,7340,L-3895314,00.html


The role includes:

  • Be part of a founding BackEnd team and tackle greatest technology challenges.
  • Responsibility for RTL2GDS flow including Floorplan, Synthesis, Place and route, clock-tree, STA, signoff (Timing, DRC, LVS, EMIR)
  • Take part in the definition of the Backend execution and methodologies.

Requirements

Requirements:

  • BSc. Degree in Electrical Engineering
  • At least 5 years’ experience as BackEnd engineer from a leading semiconductor company at advanced process technology
  • Hands-On experience in Macro level Implementation
  • Hands on experience in physical design flows and methodologies: Synthesis , floor-planning, clock building and routing
  • Hands on experience with signoff STA, LEC, DRC and EMIR
  • TCL scripting and EDA tool flow
  • Full-chip level Implementation - Advantage
  • Power and Noise analysis – Advantage
  • DFT knowledge – Advantage
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